? semiconductor components industries, llc, 2012 august, 2012 ? rev. 1 1 publication order number: ncp334/d ncp334, NCP335 2a ultra-small controlled load switch with auto-discharge path the ncp334 and NCP335 are low ron mosfet controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. indeed, due to a current consumption optimization with pmos structure, leakage currents are eliminated by isolating connected ic?s on the battery when not used. output discharge path is also embedded to eliminate residual voltages on the output rail in the NCP335. proposed in wide input voltage range from 1.2 v to 5.5 v, and a very small 0.96 x 0.96 mm wlcsp4, 0.5 mm pitch. features ? 1.2 v ? 5.5 v operating range ? 47 m p mosfet at 3.3 v ? dc current up to 2 a ? output auto ? discharge (NCP335) ? active high en pin ? wlcsp4 0.96 x 0.96 mm ? esd ratings: 4 kv human body model, 2 kv cdm, ? 250 v machine model ? these are pb ? free devices typical applications ? mobile phones ? tablets ? digital cameras ? gps ? portable devices marking diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information wlcsp4 case 567fg 1 xx = specific device code a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package xx out gnd in en 12 a b (top view) pin diagram
ncp334, NCP335 http://onsemi.com 2 b+ en ncp63xy/wdfn8 pvin 8 avin 7 sw 2 fb 4 pgnd 1 agnd 3 mode/pg 6 en 5 vout 1 2 en u5 NCP335 out a1 gnd b1 in a2 en b2 figure 1. typical application circuit pin function description pin name pin number type description in a2 power load ? switch input voltage; connect a 1 f or greater ceramic capacitor from in to gnd as close as possible to the ic. gnd b1 power ground connection. en b2 input enable input, logic high turns on power switch. out a1 output load ? switch output; connect a 1 f ceramic capacitor from out to gnd as close as pos- sible to the ic is recommended. block diagram en block control logic gate driver and soft start control in: pin a2 en: pin b2 out: pin a1 gnd: pin b1 optional: NCP335 figure 2. block diagram
ncp334, NCP335 http://onsemi.com 3 maximum ratings rating symbol value unit in, out, en, pins v en , v in, v out 0.3 to + 7.0 v from in to out pins: input/output v in, v out 0 to + 7.0 v maximum junction temperature t j ? 40 to + 125 c storage temperature range t stg ? 40 to + 150 c human body model (hbm) esd rating are (notes 1 and 2) esd hbm 4000 v machine model (mm) esd rating are (notes 1 and 2) esd mm 250 v charge device model (cdm) esd rating are (notes 1 and 2) esd cdm 2000 v latch ? up protection (note 3) ? pins in, out, en lu 100 ma moisture sensitivity (note 4) msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. according to jedec standard jesd22 ? a108. 2. this device series contains esd protection and passes the following tests: human body model (hbm) 4.0 kv per jedec standard: jesd22 ? a114 for all pins. machine model (mm) 250 v per jedec standard: jesd22 ? a115 for all pins. charge device model (cdm) 2.0 kv per jedec standard: jesd22 ? c101 for all pins. 3. latch up current maximum rating: 100 ma per jedec standard: jesd78 class ii. 4. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020. operating conditions symbol parameter conditions min typ max unit v in operational power supply 1.2 5.5 v v en enable voltage 0 5.5 t a ambient temperature range ? 40 25 + 85 c c in decoupling input capacitor 1 f c out decoupling output capacitor 1 f r ja thermal resistance junction to air wlcsp package (note 5) 100 c/w i out maximum dc current 2 a p d power dissipation rating (note 6) t a 25 c wlcsp package 0.5 w t a = 85 c wlcsp package 0.2 w 5. the r ja is dependent of the pcb heat dissipation and thermal via. 6. the maximum power dissipation ( pd ) is given by the following formula: p d t jmax t a r ja
ncp334, NCP335 http://onsemi.com 4 electrical characteristics min and max limits apply for ta between ? 40 c to +85 c for vin between 1.2 v to 5.5 v (unless otherwise noted). typical values are referenced to t a = + 25 c and v in = 4 v (unless otherwise noted). symbol parameter conditions min typ max unit power switch r ds(on) static drain ? source on ? state resistance v in = 5.5 v t a = 25 c, i = 200 ma (note 8) 38 4 0 m v in = 4.2 v t a = 25 c, i = 200 ma 42 46 v in = 3.3 v t a = 25 c, i = 200 ma 47 52 v in = 1.8 v t a = 25 c, i = 200 ma 76 87 full 100 v in = 1.2 v t a = 25 c, i = 200 ma 211 420 r dis output discharge path en = low v in = 3.3 v, NCP335 only 65 11 0 t r output rise time v in = 3.6 v c load = 1 f, r load = 25 (note 7) 71 s t f output fall time v in = 3.6 v c load = 1 f, r load = 25 (note 7) 42 s t on gate turn on v in = 3.6 v gate turn on + output rise time 116 s t en enable time v in = 3.6 v from en low to high to v out = 10% of fully on 45 s v ih high ? level input voltage 0.9 v v il low ? level input voltage 0.5 v r en pull down resistor 5 m quiescent current i q current consumption v in = 3.3 v, en = low, no load 1 a v in = 3.3 v, en= high, no load 1 a 7. parameters are guaranteed for c load and r load connected to the out pin with respect to the ground 8. guaranteed by design and characterization, not production tested. timings vout en vin figure 3. enable, rise and fall time t en t r t on t off t dis t f
ncp334, NCP335 http://onsemi.com 5 typical characteristics ? 40 c 25 c ? 25 c 50 c 0 c 85 c 300 250 200 150 100 50 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v in (v) r ds(on) (m ) figure 4. r ds(on) ( m ) vs. vin (v) 60 0 500 1000 1500 2000 2500 55 50 45 40 35 30 r ds(on) (m ) i out (ma) figure 5. r ds(on) ( m ) vs. iload (ma) at 3.6 v 62 ? 50 ? 25 0 25 50 75 125 temperature ( c) r ds(on) (m ) 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 100 figure 6. r ds(on) ( m ) vs. temperature ( c) at 3.3 v, iload 100 ma temperature ( c) r ds(on) (m ) 65 60 55 50 45 40 35 30 25 ? 50 ? 25 0 25 50 75 100 figure 7. rd s(on) ( m ) vs. temperature ( c), iload 2 a v in = 5.5 v v in = 4.2 v v in = 3.6 v v in = 3.3 v 1.8 ? 50 ? 25 0 25 50 75 125 v in (v) i in ( a) 100 figure 8. standby current ( a) versus v in (v), no load temperature = ? 40 c temperature = 25 c temperature = 85 c temperature = 125 c temperature = ? 40 c temperature = 25 c temperature = 85 c temperature = 125 c i in ( a) v in (v) 06 5 1234 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ? 0.2 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ? 0.2 figure 9. standby current ( a) versus v in (v), v out short to gnd.
ncp334, NCP335 http://onsemi.com 6 temperature = ? 40 c temperature = 25 c temperature = 85 c temperature = 125 c i in ( a) v in (v) 1.8 06 5 1234 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ? 0.2 figure 10. quiescent current ( a) versus v in (v), no load. figure 11. enable time, rise time, and ton time
ncp334, NCP335 http://onsemi.com 7 figure 12. disable time, fall time and toff time functional description overview the ncp334 ? NCP335 are high side p channel mosfet power distribution switch designed to isolate ics connected on the battery in order to save energy. the part can be turned on, with a range of battery from 1.2 v to 5.5 v. enable input enable pin is an active high. the path is opened when en pin is tied low (disable), forcing p mos switch off. the in/out path is activated with a minimum of vin of 1.2v and en forced to high level. auto discharge (NCP335 only) nmos fet is placed between the output pin and gnd, in order to discharge the application capacitor connected on out pin. the auto ? discharge is activated when en pin is set to low level (disable state). the discharge path ( pull down nmos) stays activated as long as en pin is set at low level and v in > 1.2 v. in order to limit the current across the internal discharge n ? mosfet, the typical value is set at 65 . cin and cout capacitors in and out, 1 f, at least, capacitors must be placed as close as possible the part for stability improvement.
ncp334, NCP335 http://onsemi.com 8 application information power dissipation main contributor in term of junction temperature is the power dissipation of the power mosfet. assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: p d = r ds(on) x (i out ) 2 p d = power dissipation (w) r ds(on) = power mosfet on resistance ( ) i out = output current (a) t j = p d x r ja + t a t j = junction temperature ( c r ja = package thermal resistance ( c/w) t a = ambient temperature ( c) pcb recommendations the ncp334 ? NCP335 integrate an up to 2 a rated pmos fet, and the pcb design rules must be respected to properly evacuate the heat out of the silicon. by increasing pcb area, especially around in and out pins, the r ja of the package can be decreased, allowing higher power dissipation. figure 13. routing example 1 oz, 2 layers, 100 c/w
ncp334, NCP335 http://onsemi.com 9 figure 14. routing example 2 oz, 4 layers, 60 c/w example of application definition. t j t a r ja pd r ja r ds(on) i 2 t j : junction temperature. t a : ambient temperature. r = thermal resistance between ic and air, through pcb. r ds(on) : intrinsic resistance of the ic mosfet. i: load dc current. taking into account of rtheta obtain with: 1 oz, 2 layers: 100 c/w. at 2 a, 25 c ambient temperature, r ds(on) 42 m @ v in 4.2 v, the junction temperature will be: t j t a r pd 25 0.042 2 2 100 41.8 c w taking into account of r obtain with: 2 oz, 4 layers: 60 c/w. at 2 a, 25 c ambient temperature, r ds(on) 42 m @ v in 4.2 v, the junction temperature will be: t j t a r pd 25 0.042 2 2 60 35 c. ordering information device marking package shipping ? ncp334fct2g ad wlcsp 0.96 x 0.96 mm (pb ? free) 3000 / tape & reel NCP335fct2g aa wlcsp 0.96 x 0.96 mm (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp334, NCP335 http://onsemi.com 10 package dimensions case 567fg issue o seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.54 millimeters a1 d 0.96 bsc e b 0.29 0.34 e 0.50 bsc 0.63 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 4x b 12 b a 0.05 c a a1 a2 c 0.22 0.28 0.96 bsc 0.05 c 2x top view side view bottom view note 3 e a2 0.33 ref pitch 0.25 4x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 0.50 recommended a1 package outline pitch on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp334/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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